Sdf Pipeline Fft Architecture in Vlsi

This paper explains the implementation of a R2 2 SDF Pipeline FFT Architecture using hardware description language VHDL simulated up to 20 MHz for transformation length 256-point. A hardware oriented radix-2 2 algorithm is derived by integrating a twiddle factor decomposition technique in the divide and conquer approach. Radix-2 2 algorithm has the same multiplicative complexity as radix-4 algorithm, but retains the butterfly structure of radix-2 algorithm. The single-path delay feedback architecture is used to exploit the spatial regularity in signal flow graph of an algorithm. For length-N DFT computation, the hardware requirement of proposed architecture is minimal on both dominant components: log4 N-1 complex multipliers and N-1 complex data memory. The Fast Fourier Transform (FFT) and its inverse (IFFT) are very important algorithms in signal processing, softwaredefined radio, and the most promising modulation technique; Orthogonal Frequency Division Multiplexing (OFDM).